In the original concept of RISC (Dave Patterson, UC Berkeley), one of the main ideas was that the instruction sets of core memory era computers were optimised to perform as many arithmetic and logic operations as possible per instruction because instruction fetches were time consuming compared to the speed of logic circuitry. The advocates of RISC argued that once memory access time was comparable to that of logic operations, better performance could be obtained with a simple instruction set and large register files, counting on the compiler to optimise code to perform as many operations as possible register to register without accessing memory.
Architectures such as SIMD (Illiac, etc.) and vector (Cray) went the other direction: allow a single instruction to perform processing of bulk data which could be pipelined (taking advantage of interleaving to do fetches in parallel).
Now we have most machines running on a perfect hybrid (or bastard) architecture, where the instruction set seen by the programmer or compiler is indescribably baroque but is transformed by the processor’s microcode into a very long instruction word (VLIW) internal code which the hardware actually executes with multiple functional units, register renaming, multi-level cache, and branch prediction all getting into the game to try to squeeze out more performance.