# \#address-decoding

**URL:** https://scanalyst.fourmilab.ch/tag/address-decoding/2980.md

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## [Vacuum Tube Computer Part 33: Input/Output Address Decoding](https://scanalyst.fourmilab.ch/t/vacuum-tube-computer-part-33-input-output-address-decoding/3541)

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**Author:** [@johnwalker](https://scanalyst.fourmilab.ch/u/johnwalker)\
**Replies:** 0\
**Last updated:** [31 July 2023 13:10 UTC](https://scanalyst.fourmilab.ch/t/vacuum-tube-computer-part-33-input-output-address-decoding/3541 "2023-07-31T13:10:12Z")

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Data input and output for the vacuum tube computer uses three registers, each with individually addressable bits accessible from the processor: input, output, and scratch. Each register contains eight bits…

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## [Vacuum Tube Computer Part 29: Address Line Buffers and Inverters](https://scanalyst.fourmilab.ch/t/vacuum-tube-computer-part-29-address-line-buffers-and-inverters/2127)

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**Author:** [@johnwalker](https://scanalyst.fourmilab.ch/u/johnwalker)\
**Replies:** 0\
**Last updated:** [10 October 2022 16:27 UTC](https://scanalyst.fourmilab.ch/t/vacuum-tube-computer-part-29-address-line-buffers-and-inverters/2127 "2022-10-10T16:27:27Z")

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In order to select the desired cell in the computer’s memory array, the six address lines from the processor and their logical negations must be connected to the inputs of the memory decoder array, which re…