RISC V Microcontroller for 10 Cents

SCANALYZER The Happening World
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The RISC V computer architecture was developed at the University of California, Berkeley as an open source instruction set design with modular extensions defined for features such as integer multiply and divide, floating point in single, double, and quad precision, bit manipulation, and more.

The WCH RISC-V MCU-CH32V003, which sells for ten cents in quantity, implements the RISC-V architecture with the following on-chip capabilities:

  • QingKe 32-bit RISC-V2A processor, supporting 2 levels of interrupt nesting
  • Maximum 48MHz system main frequency
  • 2KB SRAM, 16KB Flash
  • Power supply voltage: 3.3/5V
  • Multiple low-power modes: Sleep, Standby
  • Power on/off reset, programmable voltage detector
  • 1 group of 1-channel general-purpose DMA controller
  • 1 group of op-amp comparator
  • 1 group of 10-bit ADC
  • 1×16-bit advanced-control timer, 1×16-bit general-purpose timer
  • 2 WDOG, 1×32-bit SysTick
  • 1 USART interface, 1 group of I2C interface, 1 group of SPI interface
  • 18 I/O ports, mapping an external interrupt
  • 64-bit chip unique ID
  • 1-wire serial debug interface (SDI)
  • Package: TSSOP20, QFN20, SOP16, SOP8

Software can be developed in either C or RISC-V assembler and flashed into the chip’s 16 Kb program memory over a USB interface.

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This is big news to those of us who make medical devices, especially devices that would suddenly spike in demand during the supply shortages in a pandemic.

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Cheaper than an NE555

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Open source technology like RISC-V is offered free to developers, though companies often pay vendors for add-ons like enterprise features or tech support. The startup SiFive, for instance, sells licenses for its chip designs based on RISC-V. A chip instruction set is essentially the base-level in which software communicates with hardware, used to define a processor’s functions.

Meta is using RISC-V to power some of its AI computing, the company wrote in a May blog post. Running generative AI and other large AI models requires more efficient hardware systems, Meta wrote, so it designed its own rather than rely only on traditional graphics processing units. Meta declined to comment on RISC-V.

Google said it began supporting RISC-V for its Android mobile operating system last year. In October, Google announced a partnership with Qualcomm to launch RISC-V based wearable devices. In November, Google’s research division released a set of open-source tools for AI and machine-learning based on RISC-V.

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